Single-trap analysis of hot-carrier-induced gate oxide degradation in Flash memory cells

Using a test structure containing two memory cells with a shared floating gate (FG), we analyzed the processes of hot-electron-induced charge trapping in the FG oxide with a single-trap resolution. Unlike the traditional RTN-based method for single-trap study, the proposed approach allows one to detect not only the interface traps showing capture-emission events in the time domain, but also to resolve virtually all individual trapping-detrapping events in the floating gate oxide during the program-erase cycling. [Display omitted] •A common floating-gate structure was used to analyze gate oxide degradation.•Proposed differential method detects single traps in the gate oxide.•Many traps produce Vt modulations larger than predicted by 1-D model.