Stress distribution affected by nanostructures near a surface crack on a silicon chip

During the thinning and machining processes, surface defects or cracks are easily induced on a silicon chip. The defects or cracks may cause stress concentration and become one of the failure sources for silicon chips. One of our previous papers reported that the stress concentration at the crack tip on a silicon chip with nanostructure was greatly reduced for the case of four-point bending. In this paper, the finite element analysis was used to further study the effect of nanostructures on the stress distribution near the surface crack for a silicon chip. Since the stress distribution near the surface crack was our main concern for a chip under four-point bending, nanostructures were introduced in the area near the crack on the chip surface in the analysis for computational efficiency. The spacing and depth of the nanostructure, and the crack depth on the silicon chip surface were varied to access their effects on the stress distributions near the crack on the silicon chip.