Quantum circuit physical design flow for 2D nearest‐neighbor architectures

Summary The physical design process takes a netlist generated by the logic synthesis process and places and routes the netlist on a physical platform. In some physical platforms, physical qubits must be placed on a 2D grid. Each node of the grid represents a qubit. In these platforms, performing quantum gates on non‐adjacent qubits is very error prone or hard to control. Therefore, quantum gates are limited to be performed on adjacent qubits. A communication channel of swap gates needs to be constructed if the qubits in the logical circuit are not adjacent. The algorithms used for mapping of qubits on the grid have important roles in reducing the number of swap gates and thus decreasing of the circuit latency. Focusing on this issue, in this paper, a flow for physical design of quantum circuits on a 2D grid is proposed. It contains three algorithms for finding the order of qubit placement, physical qubit placement, and routing. Simulation results show that the proposed flow not only decreases the average number of swap gates by about 16% compared with the best in the literature but also improves the average runtime by about 94% compared with it. Copyright © 2017 John Wiley & Sons, Ltd. In this paper, a physical design flow was proposed for 2D nearest‐neighbor architecture. Three algorithms introduced for order finding, placement, and routing showed great performance in decreasing the number of swap gates and the runtime compared with PAQCS that is the best in the literature. Scalability is illustrated through simulations with circuits involving dozens of qubits and thousands of gates.