An Adaptive QR Decomposition Processor for Carrier-Aggregated LTE-A in 28-nm FD-SOI
This paper presents an adaptive QR decomposition (QRD) processor for five-band carrier-aggregated Long Term Evolution-Advanced downlinks. The design uses time and frequency correlation properties of wireless channels to reduce QRD computations while maintaining an uncoded bit error rate loss below 1...
Gespeichert in:
| Veröffentlicht in: | IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2017-07, Vol.64 (7), p.1914-1926 |
|---|---|
| Hauptverfasser: | , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 1926 |
|---|---|
| container_issue | 7 |
| container_start_page | 1914 |
| container_title | IEEE transactions on circuits and systems. I, Regular papers |
| container_volume | 64 |
| creator | Gangarajaiah, Rakesh Edfors, Ove Liu, Liang |
| description | This paper presents an adaptive QR decomposition (QRD) processor for five-band carrier-aggregated Long Term Evolution-Advanced downlinks. The design uses time and frequency correlation properties of wireless channels to reduce QRD computations while maintaining an uncoded bit error rate loss below 1 dB. An analysis on the performance of a linear interpolating QRD is presented, and optimum distances for different channel conditions are suggested. The Householder transform suited for spatially correlated scenarios is chosen and modified for concurrent vector rotations resulting in high throughput. Based on these, a parallel hardware architecture suitable for easy reconfigurability and low power is developed and fabricated in 28-nm fully depleted silicon-on-insulator technology. The QRD unit occupies 205k gates of logic and has a maximum throughput of 22 MQRD/s while consuming 29 mW of power. On a circuit level, the back gate feature is leveraged to double operational frequency in low time-frequency correlation channels or to lower power consumption to 1.9 mW in favorable conditions. The proposed system provides designers with multiple levels of adaptive control from architectural to circuit level for power-performance tradeoffs and is well suited for mobile devices operating on limited battery energy. |
| doi_str_mv | 10.1109/TCSI.2017.2658729 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_journals_1913548615</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>7862170</ieee_id><sourcerecordid>1913548615</sourcerecordid><originalsourceid>FETCH-LOGICAL-c428t-fb9a4e6f8faae898b4b0854f17906c5d1693d965c3ae74df7de68f3b7c9f4fc63</originalsourceid><addsrcrecordid>eNo9UU1rGzEQFaWFpm5-QOlF0LMcfX8cFydpDYa0tXMWWu3IbIhXW2md0H-fdRxyeDNzeO8NMw-hb4wuGaPuarfarpecMrPkWlnD3Qd0wZSyhFqqP55m6YgV3H5GX2p9oJQ7KtgF2jYDbrowTv0T4D9_8TXEfBhz7ac-D_h3yRFqzQWnGatQSg-FNPt9gX2YoMOb3Q1pcD9gbslwwLfXZHu3_oo-pfBY4fKtL9D97c1u9Yts7n6uV82GRMntRFLrggSdbAoBrLOtbKlVMjHjqI6qY9qJzmkVRQAju2Q60DaJ1kSXZIpaLNDm7FufYTy2fiz9IZT_PofePx7HGe0MX8GDEVRJyb3VrfCSdsK7VkZvRFJMiflPc12gH2e7seR_R6iTf8jHMswXeOaYUNLqVxY7s2LJtRZI72sZ9aco_CkKf4rCv0Uxa76fNT0AvPON1ZwZKl4A8fqB4g</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1913548615</pqid></control><display><type>article</type><title>An Adaptive QR Decomposition Processor for Carrier-Aggregated LTE-A in 28-nm FD-SOI</title><source>IEEE Electronic Library (IEL)</source><creator>Gangarajaiah, Rakesh ; Edfors, Ove ; Liu, Liang</creator><creatorcontrib>Gangarajaiah, Rakesh ; Edfors, Ove ; Liu, Liang</creatorcontrib><description>This paper presents an adaptive QR decomposition (QRD) processor for five-band carrier-aggregated Long Term Evolution-Advanced downlinks. The design uses time and frequency correlation properties of wireless channels to reduce QRD computations while maintaining an uncoded bit error rate loss below 1 dB. An analysis on the performance of a linear interpolating QRD is presented, and optimum distances for different channel conditions are suggested. The Householder transform suited for spatially correlated scenarios is chosen and modified for concurrent vector rotations resulting in high throughput. Based on these, a parallel hardware architecture suitable for easy reconfigurability and low power is developed and fabricated in 28-nm fully depleted silicon-on-insulator technology. The QRD unit occupies 205k gates of logic and has a maximum throughput of 22 MQRD/s while consuming 29 mW of power. On a circuit level, the back gate feature is leveraged to double operational frequency in low time-frequency correlation channels or to lower power consumption to 1.9 mW in favorable conditions. The proposed system provides designers with multiple levels of adaptive control from architectural to circuit level for power-performance tradeoffs and is well suited for mobile devices operating on limited battery energy.</description><identifier>ISSN: 1549-8328</identifier><identifier>EISSN: 1558-0806</identifier><identifier>DOI: 10.1109/TCSI.2017.2658729</identifier><identifier>CODEN: ITCSCH</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Adaptive control ; Adaptive processing ; Batteries ; Bit error rate ; Channels ; Circuit design ; Computer architecture ; Control systems ; Correlation ; Detectors ; Downlinking ; Electrical Engineering, Electronic Engineering, Information Engineering ; Electronic devices ; Elektroteknik och elektronik ; Engineering and Technology ; Error analysis ; Gates ; Gates (circuits) ; Hardware ; Householder transformations ; Interpolation ; Logic ; Long Term Evolution-Advanced (LTE-A) ; LTE-A, QRD, Adaptive processing ; Microprocessors ; MIMO ; OFDM ; Power consumption ; QR decomposition (QRD) ; Silicon ; SOI (semiconductors) ; Teknik ; Time-frequency analysis</subject><ispartof>IEEE transactions on circuits and systems. I, Regular papers, 2017-07, Vol.64 (7), p.1914-1926</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2017</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c428t-fb9a4e6f8faae898b4b0854f17906c5d1693d965c3ae74df7de68f3b7c9f4fc63</citedby><cites>FETCH-LOGICAL-c428t-fb9a4e6f8faae898b4b0854f17906c5d1693d965c3ae74df7de68f3b7c9f4fc63</cites><orcidid>0000-0002-3839-4506</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/7862170$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>230,314,777,781,793,882,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/7862170$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttps://lup.lub.lu.se/record/e7305442-86b3-40d3-9b4c-73f515355815$$DView record from Swedish Publication Index$$Hfree_for_read</backlink></links><search><creatorcontrib>Gangarajaiah, Rakesh</creatorcontrib><creatorcontrib>Edfors, Ove</creatorcontrib><creatorcontrib>Liu, Liang</creatorcontrib><title>An Adaptive QR Decomposition Processor for Carrier-Aggregated LTE-A in 28-nm FD-SOI</title><title>IEEE transactions on circuits and systems. I, Regular papers</title><addtitle>TCSI</addtitle><description>This paper presents an adaptive QR decomposition (QRD) processor for five-band carrier-aggregated Long Term Evolution-Advanced downlinks. The design uses time and frequency correlation properties of wireless channels to reduce QRD computations while maintaining an uncoded bit error rate loss below 1 dB. An analysis on the performance of a linear interpolating QRD is presented, and optimum distances for different channel conditions are suggested. The Householder transform suited for spatially correlated scenarios is chosen and modified for concurrent vector rotations resulting in high throughput. Based on these, a parallel hardware architecture suitable for easy reconfigurability and low power is developed and fabricated in 28-nm fully depleted silicon-on-insulator technology. The QRD unit occupies 205k gates of logic and has a maximum throughput of 22 MQRD/s while consuming 29 mW of power. On a circuit level, the back gate feature is leveraged to double operational frequency in low time-frequency correlation channels or to lower power consumption to 1.9 mW in favorable conditions. The proposed system provides designers with multiple levels of adaptive control from architectural to circuit level for power-performance tradeoffs and is well suited for mobile devices operating on limited battery energy.</description><subject>Adaptive control</subject><subject>Adaptive processing</subject><subject>Batteries</subject><subject>Bit error rate</subject><subject>Channels</subject><subject>Circuit design</subject><subject>Computer architecture</subject><subject>Control systems</subject><subject>Correlation</subject><subject>Detectors</subject><subject>Downlinking</subject><subject>Electrical Engineering, Electronic Engineering, Information Engineering</subject><subject>Electronic devices</subject><subject>Elektroteknik och elektronik</subject><subject>Engineering and Technology</subject><subject>Error analysis</subject><subject>Gates</subject><subject>Gates (circuits)</subject><subject>Hardware</subject><subject>Householder transformations</subject><subject>Interpolation</subject><subject>Logic</subject><subject>Long Term Evolution-Advanced (LTE-A)</subject><subject>LTE-A, QRD, Adaptive processing</subject><subject>Microprocessors</subject><subject>MIMO</subject><subject>OFDM</subject><subject>Power consumption</subject><subject>QR decomposition (QRD)</subject><subject>Silicon</subject><subject>SOI (semiconductors)</subject><subject>Teknik</subject><subject>Time-frequency analysis</subject><issn>1549-8328</issn><issn>1558-0806</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9UU1rGzEQFaWFpm5-QOlF0LMcfX8cFydpDYa0tXMWWu3IbIhXW2md0H-fdRxyeDNzeO8NMw-hb4wuGaPuarfarpecMrPkWlnD3Qd0wZSyhFqqP55m6YgV3H5GX2p9oJQ7KtgF2jYDbrowTv0T4D9_8TXEfBhz7ac-D_h3yRFqzQWnGatQSg-FNPt9gX2YoMOb3Q1pcD9gbslwwLfXZHu3_oo-pfBY4fKtL9D97c1u9Yts7n6uV82GRMntRFLrggSdbAoBrLOtbKlVMjHjqI6qY9qJzmkVRQAju2Q60DaJ1kSXZIpaLNDm7FufYTy2fiz9IZT_PofePx7HGe0MX8GDEVRJyb3VrfCSdsK7VkZvRFJMiflPc12gH2e7seR_R6iTf8jHMswXeOaYUNLqVxY7s2LJtRZI72sZ9aco_CkKf4rCv0Uxa76fNT0AvPON1ZwZKl4A8fqB4g</recordid><startdate>20170701</startdate><enddate>20170701</enddate><creator>Gangarajaiah, Rakesh</creator><creator>Edfors, Ove</creator><creator>Liu, Liang</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>ADTPV</scope><scope>AOWAS</scope><scope>D95</scope><orcidid>https://orcid.org/0000-0002-3839-4506</orcidid></search><sort><creationdate>20170701</creationdate><title>An Adaptive QR Decomposition Processor for Carrier-Aggregated LTE-A in 28-nm FD-SOI</title><author>Gangarajaiah, Rakesh ; Edfors, Ove ; Liu, Liang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c428t-fb9a4e6f8faae898b4b0854f17906c5d1693d965c3ae74df7de68f3b7c9f4fc63</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><topic>Adaptive control</topic><topic>Adaptive processing</topic><topic>Batteries</topic><topic>Bit error rate</topic><topic>Channels</topic><topic>Circuit design</topic><topic>Computer architecture</topic><topic>Control systems</topic><topic>Correlation</topic><topic>Detectors</topic><topic>Downlinking</topic><topic>Electrical Engineering, Electronic Engineering, Information Engineering</topic><topic>Electronic devices</topic><topic>Elektroteknik och elektronik</topic><topic>Engineering and Technology</topic><topic>Error analysis</topic><topic>Gates</topic><topic>Gates (circuits)</topic><topic>Hardware</topic><topic>Householder transformations</topic><topic>Interpolation</topic><topic>Logic</topic><topic>Long Term Evolution-Advanced (LTE-A)</topic><topic>LTE-A, QRD, Adaptive processing</topic><topic>Microprocessors</topic><topic>MIMO</topic><topic>OFDM</topic><topic>Power consumption</topic><topic>QR decomposition (QRD)</topic><topic>Silicon</topic><topic>SOI (semiconductors)</topic><topic>Teknik</topic><topic>Time-frequency analysis</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Gangarajaiah, Rakesh</creatorcontrib><creatorcontrib>Edfors, Ove</creatorcontrib><creatorcontrib>Liu, Liang</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>SwePub</collection><collection>SwePub Articles</collection><collection>SWEPUB Lunds universitet</collection><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Gangarajaiah, Rakesh</au><au>Edfors, Ove</au><au>Liu, Liang</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>An Adaptive QR Decomposition Processor for Carrier-Aggregated LTE-A in 28-nm FD-SOI</atitle><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle><stitle>TCSI</stitle><date>2017-07-01</date><risdate>2017</risdate><volume>64</volume><issue>7</issue><spage>1914</spage><epage>1926</epage><pages>1914-1926</pages><issn>1549-8328</issn><eissn>1558-0806</eissn><coden>ITCSCH</coden><abstract>This paper presents an adaptive QR decomposition (QRD) processor for five-band carrier-aggregated Long Term Evolution-Advanced downlinks. The design uses time and frequency correlation properties of wireless channels to reduce QRD computations while maintaining an uncoded bit error rate loss below 1 dB. An analysis on the performance of a linear interpolating QRD is presented, and optimum distances for different channel conditions are suggested. The Householder transform suited for spatially correlated scenarios is chosen and modified for concurrent vector rotations resulting in high throughput. Based on these, a parallel hardware architecture suitable for easy reconfigurability and low power is developed and fabricated in 28-nm fully depleted silicon-on-insulator technology. The QRD unit occupies 205k gates of logic and has a maximum throughput of 22 MQRD/s while consuming 29 mW of power. On a circuit level, the back gate feature is leveraged to double operational frequency in low time-frequency correlation channels or to lower power consumption to 1.9 mW in favorable conditions. The proposed system provides designers with multiple levels of adaptive control from architectural to circuit level for power-performance tradeoffs and is well suited for mobile devices operating on limited battery energy.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCSI.2017.2658729</doi><tpages>13</tpages><orcidid>https://orcid.org/0000-0002-3839-4506</orcidid></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1549-8328 |
| ispartof | IEEE transactions on circuits and systems. I, Regular papers, 2017-07, Vol.64 (7), p.1914-1926 |
| issn | 1549-8328 1558-0806 |
| language | eng |
| recordid | cdi_proquest_journals_1913548615 |
| source | IEEE Electronic Library (IEL) |
| subjects | Adaptive control Adaptive processing Batteries Bit error rate Channels Circuit design Computer architecture Control systems Correlation Detectors Downlinking Electrical Engineering, Electronic Engineering, Information Engineering Electronic devices Elektroteknik och elektronik Engineering and Technology Error analysis Gates Gates (circuits) Hardware Householder transformations Interpolation Logic Long Term Evolution-Advanced (LTE-A) LTE-A, QRD, Adaptive processing Microprocessors MIMO OFDM Power consumption QR decomposition (QRD) Silicon SOI (semiconductors) Teknik Time-frequency analysis |
| title | An Adaptive QR Decomposition Processor for Carrier-Aggregated LTE-A in 28-nm FD-SOI |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-19T17%3A22%3A31IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=An%20Adaptive%20QR%20Decomposition%20Processor%20for%20Carrier-Aggregated%20LTE-A%20in%2028-nm%20FD-SOI&rft.jtitle=IEEE%20transactions%20on%20circuits%20and%20systems.%20I,%20Regular%20papers&rft.au=Gangarajaiah,%20Rakesh&rft.date=2017-07-01&rft.volume=64&rft.issue=7&rft.spage=1914&rft.epage=1926&rft.pages=1914-1926&rft.issn=1549-8328&rft.eissn=1558-0806&rft.coden=ITCSCH&rft_id=info:doi/10.1109/TCSI.2017.2658729&rft_dat=%3Cproquest_RIE%3E1913548615%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=1913548615&rft_id=info:pmid/&rft_ieee_id=7862170&rfr_iscdi=true |