An Adaptive QR Decomposition Processor for Carrier-Aggregated LTE-A in 28-nm FD-SOI

This paper presents an adaptive QR decomposition (QRD) processor for five-band carrier-aggregated Long Term Evolution-Advanced downlinks. The design uses time and frequency correlation properties of wireless channels to reduce QRD computations while maintaining an uncoded bit error rate loss below 1 dB. An analysis on the performance of a linear interpolating QRD is presented, and optimum distances for different channel conditions are suggested. The Householder transform suited for spatially correlated scenarios is chosen and modified for concurrent vector rotations resulting in high throughput. Based on these, a parallel hardware architecture suitable for easy reconfigurability and low power is developed and fabricated in 28-nm fully depleted silicon-on-insulator technology. The QRD unit occupies 205k gates of logic and has a maximum throughput of 22 MQRD/s while consuming 29 mW of power. On a circuit level, the back gate feature is leveraged to double operational frequency in low time-frequency correlation channels or to lower power consumption to 1.9 mW in favorable conditions. The proposed system provides designers with multiple levels of adaptive control from architectural to circuit level for power-performance tradeoffs and is well suited for mobile devices operating on limited battery energy.