Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology

Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology

This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS technology. The latch comprises three interlocked single-node-upset-resilient cells and each of the cells mainly consists of three mutually feeding back Muller C-elements. Simulation results demonstrate the double-n...

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Veröffentlicht in:IEEE transactions on very large scale integration (VLSI) systems 2017-06, Vol.25 (6), p.1978-1982
Hauptverfasser: Yan, Aibin, Huang, Zhengfeng, Yi, Maoxiang, Xu, Xiumin, Ouyang, Yiming, Liang, Huaguo
Format: Artikel
Sprache:eng
Schlagworte:
Circuit reliability
CMOS
Digital cameras
double-node upset (DNU)
Energy conservation
Feedback loop
Integrated circuit interconnections
Inverters
Latches
Power dissipation
radiation hardening
Radiation hardening (electronics)
Robustness
single-node upset (SNU)
soft error
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Beschreibung
Zusammenfassung:This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS technology. The latch comprises three interlocked single-node-upset-resilient cells and each of the cells mainly consists of three mutually feeding back Muller C-elements. Simulation results demonstrate the double-node upset resilience and a 73.0% delay-power-area product saving on average compared with the up-to-date DNURL designs.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2017.2655079