Optimal Modulation Algorithm for Hybrid Clamped Three-Level Inverter

Experimental results obtained by DSP-based implementation of the controller on 1 MW prototype show good performance in terms of DC-bus voltages regulation (small neutral point potential function and low DC ripple coefficient) and good sinusoidal current. With the development of power electronic tech...

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Veröffentlicht in:Telkomnika 2016-12, Vol.14 (4), p.1253
Hauptverfasser: Liu, Yi, Tan, Guojun, He, Xiaoqun
Format: Artikel
Sprache:eng
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Zusammenfassung:Experimental results obtained by DSP-based implementation of the controller on 1 MW prototype show good performance in terms of DC-bus voltages regulation (small neutral point potential function and low DC ripple coefficient) and good sinusoidal current. With the development of power electronic technology, in [4-7], multilevel technology has been widely studied in the high-voltage and high-power system, grid-connected wind power system, active power filters, and many other fields. [...]large-scale application of multilevel topology is subjected to the unbalance voltages of capacitors in DC-bus and the turn-offover-voltage for power switching devices [13- 15], and diode clamped three-level inverter is no exception [16]. Compared to three phased diode clamped three-level inverter, three clamped capacitors are added to three clamped legs. [...]it can restrain the fluctuations of DC-bus neutral potential, realize the bidirectional current flow and restrain the over-voltages of the power switching devices by charging or discharging clamped capacitors and feasible modulation algorithms. Concentrated on the three phased HCTLI, a new PWM control algorithm is proposed by different optimal combination of neutral small vectors without the use of three clamped capacitor voltages measured in this paper. SA=1- indicates the on state of power switches S3a, S4a with S1a, S2a off. [...]the output voltage could be controlled by the switch states described above. 1) SA=1+ state In SA=1+, the S1a, S2a are turned on and S3a, S4a offas shown in Figure 2(a). [9] Mathew J, Rajeevan PP, Mathew K, Azeez NA, Gopakumar K. Multilevel dodecagonal voltage space vector generation using flying capacitor topology...
ISSN:1693-6930
2302-9293
DOI:10.12928/telkomnika.v14i4.3871