Analysis of 4H-SiC MOS capacitors on macro-stepped surfaces

Analysis of 4H-SiC MOS capacitors on macro-stepped surfaces

In this study, we analyze the electrical properties of MOS capacitors fabricated on different surface morphologies. Comparing a standard, low-roughness (

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Bibliographische Detailangaben
Veröffentlicht in:2016 European Conference on Silicon Carbide & Related Materials (ECSCRM) 2017-05, Vol.897, p.1-1
Hauptverfasser: Camarda, Massimo, Woerle, Judith, Souliere, Veronique, Ferro, Gabriel, Sigg, Hans, Grossner, Ulrike, Gobrecht, Jens
Format: Artikel
Sprache:eng
Schlagworte:
Annealing
Capacitors
CVD
Electrical properties
faceting
interface state traps
liquid silicon
macrosteps
MOSFET
Rough surfaces
Roughness
Silicon
Silicon carbide
step bunching
Surface morphology
Surface roughness
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Zusammenfassung:In this study, we analyze the electrical properties of MOS capacitors fabricated on different surface morphologies. Comparing a standard, low-roughness (
ISSN:1662-9752
0255-5476
1662-9752
DOI:10.4028/www.scientific.net/MSF.897.107