Architecture and design methodology of on-chip debug module for multi-cores system

This paper not only proposes an architecture description but also presents design methodology of on-chip debug module aiming at multi-cores system. Through the internal priority register setting, different cores can be set with or without different priory level, by which the different debugging structure can be realized. Internal arbitration mechanism either handles the competition between different master cores having the same priority level to access the same slave cores, or decides the access order for different master cores with the different priority level. All these techniques are integrated to make the on-chip debugging operation more efficient and flexible. Keywords: on-chip debug, arbitration, poriority setting, multi-cores sytem