Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology

This work presents the co-integration of resistive random access memory crossbars within a 180 nm Read-Write CMOS chip. TaO x -based ReRAMs have been fabricated and characterized with materials and process steps compatible with the CMOS Back-End-of-the-Line. Two different strategies, consisting in insertion of an Al 2 O 3 tunnel barrier layer and the design of a dedicated CMOS read circuit, have been developed in order to increase the cell high-to-low resistance ratio of a factor of 1000 and to reduce the sneak-path current effects by one order of magnitude. The ReRAM cells have been integrated directly on a standard CMOS foundry chip, enabling low cost ReRAM-CMOS integration. The integrated memories show a set and reset voltages of -1 and 1.3 V, respectively. The measured operating voltages are compatible for low-voltage applications.