SFERA: An Integrated Circuit for the Readout of X and [Formula Omitted]-Ray Detectors

In this work we present SFERA, a low-noise fully-programmable 16 channel readout ASIC designed for both X- and [Formula Omitted]-ray spectroscopy and imaging applications. The chip is designed to process signals coming from solid-state detectors and CMOS preamplifiers. The design has been guided by the use of Silicon Drift Detectors (SDDs) and CUBE charge sensitive amplifiers (CSAs), although we consider the ASIC sufficiently versatile to be used with other types of detectors. Five different gains are implemented, namely [Formula Omitted], [Formula Omitted], [Formula Omitted], [Formula Omitted] and [Formula Omitted], considering the input connected to a 25 fF feedback capacitance CMOS preamplifier. Filter peaking times ([Formula Omitted]) are also programmable among 0.5, 1, 2, 3, 4 and 6 [Formula Omitted]. Each readout channel is the cascade of a 9th order semi-Gaussian shaping-amplifier (SA) and a peak detector (PKS), followed by a dedicated pile-up rejection (PUR) digital logic. Three data multiplexing strategies are implemented: the so-called polling X , intended for high-rate X-ray applications, the polling [Formula Omitted], for scintillation light detection and the sparse , for signals derandomization. The spectroscopic characterization has shown an energy resolution of 122.1 eV FWHM on the Mn-[Formula Omitted] line of an 55Fe X-ray source using a [Formula Omitted] SDD cooled at -35 °C at [Formula Omitted] filter peaking time. The measured resolution is 130 eV at the peaking time of 500 ns. At 1 Mcps input count rate and 500 ns peaking time, we have measured 42% of processed events at the output of the ASIC after the PUR selection. Output data can be digitized on-chip by means of an embedded 12-bit successive-approximation ADC. The effective resolution of the data converter is 10.75-bit when operated at 4.5 MS/s. The chosen technology is the AMS [Formula Omitted] CMOS and the chip area occupancy is [Formula Omitted].