Design and Layout Strategy in the 60-V Power pLDMOS With Drain-End Modulated Engineering of Reliability Considerations

This study reports the impacts of various drain end layouts on the reliability and electrical performance of 60V p-channel laterally diffused metal-oxide-semiconductor (pLDMOS) FETs. For effectively improving the reliability, drain-end "N-P-N" and "P-N-P" permutated pLDMOSs embedded with silicon-controlled rectifiers (pLDMOS-SCRs) with discrete regulated structures in the drain strap were manufactured using a 0.25-μm BCD process. According to transmission-line pulse data, the I t2 value is very low (only 0.644 A) for a pure pLDMOS transistor. However, embedding an SCR in the drain end results in a decrease in V t1 , V h , and V BK and increase in I t2 values (>7 A), even for N-P-N and P-N-P drain-end arranged types. In addition, the I t2 capability of the nonbutted-contact pLDMOS-SCR devices is satisfactory. By contrast, N-P-N and P-N-P stripe-type devices with the highest N + /P + area ratio have less favorable electrical properties and lower anti-latchup (LU) immunity compared with a pure pLDMOS. In addition, the V h (and VBK) improvement of the P-N-P stripe type is more than 278% (and 23.7%) compared with the N-P-N stripe type. Therefore, pLDMOS-SCRs with a P-N-P stripe-type structure are a potential candidate for enhancing electrostatic discharge, LU immunities and electrical performance.