Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies

This paper presents two ultra-high-speed SerDes dedicated for PAM4 and NRZ data. The PAM4 TX incorporates an output driver with 3-tap FFE and adjustable weighting to deliver clean outputs at 4 levels, and the PAM4 RX employs a purely linear full-rate CDR and CTLE/1-tap DFE combination to recover and...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2015-09, Vol.50 (9), p.2061-2073
Hauptverfasser:	Lee, Jri, Ping-Chuan Chiang, Pen-Jui Peng, Li-Yang Chen, Chih-Chi Weng
Format:	Artikel
Sprache:	eng
Schlagworte:	Bandwidth Clock and data recovery (CDR) Clocks Decision feedback equalizers equalizer high-speed serial link NRZ Optical signal processing PAM4 Phase locked loops phase-locked loop (PLL) SerDes Signal to noise ratio transceiver (TRX) Transceivers
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Beschreibung
Zusammenfassung:	This paper presents two ultra-high-speed SerDes dedicated for PAM4 and NRZ data. The PAM4 TX incorporates an output driver with 3-tap FFE and adjustable weighting to deliver clean outputs at 4 levels, and the PAM4 RX employs a purely linear full-rate CDR and CTLE/1-tap DFE combination to recover and demultiplex the data. NRZ TX includes a tree-structure MUX with built-in PLL and phase aligner. NRZ RX adopts linear PD with special vernier technique to handle the 56 Gb/s input data. All chips have been verified in silicon with reasonable performance, providing prospective design examples for next-generation 400 GbE.
ISSN:	0018-9200 1558-173X
DOI:	10.1109/JSSC.2015.2433269