A High-Throughput Neural Network Accelerator

A High-Throughput Neural Network Accelerator

The authors designed an accelerator architecture for large-scale neural networks, with an emphasis on the impact of memory on accelerator design, performance, and energy. In this article, they present a concrete design at 65 nm that can perform 496 16-bit fixed-point operations in parallel every 1.0...

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Veröffentlicht in:IEEE MICRO 2015-05, Vol.35 (3), p.24-32
Hauptverfasser: Tianshi Chen, Zidong Du, Ninghui Sun, Jia Wang, Chengyong Wu, Yunji Chen, Temam, Olivier
Format: Artikel
Sprache:eng
Schlagworte:
Accelerators
Algorithms
Architecture
Artificial neural networks
Computer architecture
Computer memory
Design engineering
Efficient consumer response
Embedded systems
Evolution
Graphics processing units
hardware accelerator
Machine learning
neural network
Neural networks
State of the art
Tasks
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Beschreibung
Zusammenfassung:The authors designed an accelerator architecture for large-scale neural networks, with an emphasis on the impact of memory on accelerator design, performance, and energy. In this article, they present a concrete design at 65 nm that can perform 496 16-bit fixed-point operations in parallel every 1.02 ns, that is, 452 gop/s, in a 3.02mm 2 , 485-mw footprint (excluding main memory accesses).
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2015.41