A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS

A 40 MHz-BW 10 bit two-step VCO-based Delta-Sigma ADC is presented. With the open-loop structure and highly digital building blocks, a robust performance, high bandwidth and high power efficiency are achieved. The nonlinearities of the coarse and the fine VCO-based quantizers are mitigated by distortion cancellation and voltage swing reduction schemes respectively. Because of the intrinsic DEM of the VCO-based quantizer output, the matching requirement of the DAC cells is greatly relaxed. The experimental results in 40 nm CMOS show that, with 1.6 GHz sampling frequency, the proposed ADC reaches 59.5 dB SNDR and 67.7 dB SFDR for 40 MHz bandwidth. The power consumption is only 2.57 mW under 0.9 V power supply, corresponding the best FoM (42 fJ/step) among high bandwidth ( 20 MHz) DS ADCs.