A 0.5-V, 1.47- \mu\hbox 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation

A 0.5-V, 1.47- \mu\hbox 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation

A 13-bit successive approximation analog-to-digital converter (ADC) is presented for an ultralow-power sensor interface. Capacitor error compensation is achieved by swapping the roles of two identical capacitor banks in a digital-to-analog converter. The ADC is implemented in a standard 0.13-μm CMOS...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2014-11, Vol.61 (11), p.840-844
Hauptverfasser: Ha, Hyunsoo, Lee, Seon-Kyoo, Kim, Byungsub, Park, Hong-June, Sim, Jae-Yoon
Format: Artikel
Sprache:eng
Schlagworte:
Calibration
Capacitors
CMOS integrated circuits
Dissipation
Electric potential
Error compensation
Figure of merit
Measurement uncertainty
Noise
Sampling
Synthetic aperture radar
Thermal noise
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A 13-bit successive approximation analog-to-digital converter (ADC) is presented for an ultralow-power sensor interface. Capacitor error compensation is achieved by swapping the roles of two identical capacitor banks in a digital-to-analog converter. The ADC is implemented in a standard 0.13-μm CMOS. With a single supply voltage of 0.5 V and a rail-to-rail conversion range, the ADC dissipates 1.47 μW at a sampling rate of 40 kS/s. It shows a figure of merit of 17.9 fJ/conversion-step with an effective number of 11.0 bits.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2014.2350378