Write Assist Circuit to Cater Reliability and Floating Bit Line Problem of Negative Bit Line Assist Technique for Single or Multiport Static Random Access Memory

We propose adaptive negative bit line write assist (WA) circuit for static random access memory (SRAM). It provides controlled overdrive voltage (or negative bump) across the full range of operating voltage. This allows dynamic voltage and frequency scaling without penalizing the reliability at high...

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Veröffentlicht in:IEEE transactions on very large scale integration (VLSI) systems 2014-11, Vol.22 (11), p.2350-2356
Hauptverfasser: Dhori, Kedar Janardan, Kumar, Vinay, Rawat, Harsh
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Sprache:eng
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