Write Assist Circuit to Cater Reliability and Floating Bit Line Problem of Negative Bit Line Assist Technique for Single or Multiport Static Random Access Memory

We propose adaptive negative bit line write assist (WA) circuit for static random access memory (SRAM). It provides controlled overdrive voltage (or negative bump) across the full range of operating voltage. This allows dynamic voltage and frequency scaling without penalizing the reliability at high...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on very large scale integration (VLSI) systems 2014-11, Vol.22 (11), p.2350-2356
Hauptverfasser: Dhori, Kedar Janardan, Kumar, Vinay, Rawat, Harsh
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:We propose adaptive negative bit line write assist (WA) circuit for static random access memory (SRAM). It provides controlled overdrive voltage (or negative bump) across the full range of operating voltage. This allows dynamic voltage and frequency scaling without penalizing the reliability at higher voltage and temperature. Design is implemented in CMOS 32NM low power technology for dual port (DP) SRAM bit cell 0.390u2 (DP390) having a normal operating range from 0.9 to 1.1 V, extended to 0.75-1.1 V by utilizing proposed WA circuit. This design has an area overhead of 4.5%. Write cycle performance improvement and dynamic power reduction achieved is 10% and 8%, respectively, at 0.9 V with respect to the design without WA.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2013.2288934