A 2.5-GHz Receiver Front-End With [Formula Omitted]-Boosted Post-LNA [Formula Omitted]-Path Filtering in 40-nm CMOS

This paper presents the analysis, design, and measurements of a 2.5-GHz receiver front-end in a 40-nm CMOS technology. The front-end utilizes RLC-resonator quality factor [Formula Omitted] boosting and four-phase [Formula Omitted]-path filtering to improve the blocker filtering capabilities of the low-noise amplifier (LNA). Systematic analysis is performed in order to obtain a thorough design approach. Particular attention is paid to the passive mixer switches in the RLC case, for which we show that minimum switch resistance does not provide best noise figure (NF), nor best relative blocker attenuation. Moreover, the [Formula Omitted]-path filter extends the stable operating region of a [Formula Omitted]-boosted LNA, and adding a noisy [Formula Omitted]-boosting circuit can actually improve the receiver NF in practical realizations. The experimental CMOS front-end is flip-chip packaged, and a parasitic-aware input matching method for the electrostatic-discharge-protected LNA is proposed, analyzed, and verified. In nominal operation, the programmable front-end achieves a measured gain of 39 dB, an NF of 3.5 dB, and an out-of-band input-referred third order intercept point of [Formula Omitted], while consuming 48 mA from a 1.1-V supply.