Evaluation and Solutions for P/E Window Instability Induced by Electron Trapping in High- \kappa Intergate Dielectrics of Flash Memory Cells

High density of electron trapping in high-κ intergate dielectric (IGD) materials remains a major concern for planar memory cells with either poly-Si or hybrid floating gates (FGs). In this paper, for the first time, using the ultrafast I-V measurements, it is demonstrated that a significant portion of the P/E windows are actually contributed by electrons trapped initially in the high-κ IGD stacks during program/erase, and then discharged to FG or control gate during verification. More importantly, it is demonstrated, for the first time, that this fast charge transition can be suppressed using novel multilayer high-κ IGD structures, and the fast window instability can be eliminated.