A 0.39-0.44 THz 2x4 Amplifier-Quadrupler Array With Peak EIRP of 3-4 dBm

This paper presents a CMOS amplifier-multiplier-antenna array capable of generating an EIRP of 3-4 dBm at 420 GHz. The chip is built using a 45-nm CMOS SOI process, and efficient on-chip antennas are used to extract the power out of the chip. The design is based on a 90-110 GHz distribution network...

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Veröffentlicht in:IEEE transactions on microwave theory and techniques 2013-12, Vol.61 (12), p.4483-4491
Hauptverfasser: Golcuk, Fatih, Gurbuz, Ozan Dogan, Rebeiz, Gabriel M.
Format: Artikel
Sprache:eng
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Zusammenfassung:This paper presents a CMOS amplifier-multiplier-antenna array capable of generating an EIRP of 3-4 dBm at 420 GHz. The chip is built using a 45-nm CMOS SOI process, and efficient on-chip antennas are used to extract the power out of the chip. The design is based on a 90-110 GHz distribution network with splitters and amplifiers, and a balanced quadrupler capable of delivering up > 100 μW of power at 370-430 GHz. The amplifier-multiplier concept is proven on a 2×4 array, and it can be also scaled to any N×M array using additional W-band splitters and amplifiers.
ISSN:0018-9480
1557-9670
DOI:10.1109/TMTT.2013.2287493