An Optimized multiplier using reversible logic gates

Reversible logic is very essential for the construction of low power, low loss computational structures which are very essential for the construction of arithmetic circuits used in quantum computation, nano technology and other low power digital circuits. In this paper two designs of an optimized parallel multiplier circuit using reversible logic gates is presented. Multipliers are very essential for the construction of various computational units of a quantum computer. Duplication of operand bits are achieved using two gates namely BVF gate and CFO gate. The multiplier circuit uses DPG gates and a new 4 X 4 reversible logic gate called PPG gate. The proposed work is best compared to the other existing circuits.