A Co-Design Approach for SET Mitigation in Embedded Systems

A Co-Design Approach for SET Mitigation in Embedded Systems

We propose a new methodology for hardware/software co-design of embedded systems which is specifically aimed to mitigate SET effects. A hardening infrastructure is used to generate different versions of the design using several combinations of hardware and software hardening which are evaluated with...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on nuclear science 2012-08, Vol.59 (4), p.1034-1039
Hauptverfasser: Lindoso, Almudena, Entrena, Luis, Millan, Enrique San, Cuenca-Asensi, Sergio, Martinez-Alvarez, Antonio, Restrepo-Calle, Felipe
Format: Artikel
Sprache:eng
Schlagworte:
Benchmark testing
Circuit faults
Clocks
Co-design
Computer programs
Design engineering
Error analysis
Fault tolerance
Hardening
Hardware
Infrastructure
Methodology
radiation effects
Registers
single event transient
soft error
Software
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:We propose a new methodology for hardware/software co-design of embedded systems which is specifically aimed to mitigate SET effects. A hardening infrastructure is used to generate different versions of the design using several combinations of hardware and software hardening which are evaluated with respect to SET effects. The advantages of the proposed approach are demonstrated by means of a case study.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2011.2182524