Design-Dependent Process Monitoring for Wafer Manufacturing and Test Cost Reduction

Short-loop process monitoring structures (usually simple device I-V, C-V measurements made after M1 fabrication) are commonly put in wafer scribelines. These test structures are almost always design independent and measured or monitored by the foundry to keep track of process deviations. We propose a design-dependent process monitoring strategy that can accurately predict design performance based on I eff -based delay and I off -based leakage power estimates. Further, we use the predicted delay and power for early yield estimation to: 1) prune bad wafers to save test and back-end manufacturing costs, and 2) prune bad dies to save testing costs. Combining chip pruning with wafer pruning, we can reduce the cost per good chip by up to 13%. Such design-dependent process monitoring can help reduce process optimization effort, and enable quicker yield ramp besides saving testing and manufacturing costs.