Separate Extraction of Source, Drain, and Substrate Resistances in MOSFETs With Parasitic Junction Current Method

The separate extraction of asymmetric source ( R S ) and drain ( R D ) resistances caused by the variations in the layout, process, and device degradation is important in the practical modeling and characterization of MOSFETs and their integrated circuits. We propose a simple "parasitic junctio...

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Veröffentlicht in:	IEEE electron device letters 2010-11, Vol.31 (11), p.1190-1192
Hauptverfasser:	Bae, Hagyoul, Baek, Seok Cheon, Lee, Sunyeong, Jang, Jaeman, Shin, Ja Sun, Yun, Daeyoun, Kim, Hyojong, Kim, Dae Hwan, Kim, Dong Myong
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Asymmetry Degradation Design. Technologies. Operation analysis. Testing Devices Drain resistance Drains Electronics Exact sciences and technology Extraction Integrated circuit modeling Integrated circuits Junctions Logic gates Mathematical models MOSFET MOSFETs parameter extraction parasitic junction parasitic resistance Resistance Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices source resistance substrate resistance Substrates Transistors
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Beschreibung
Zusammenfassung:	The separate extraction of asymmetric source ( R S ) and drain ( R D ) resistances caused by the variations in the layout, process, and device degradation is important in the practical modeling and characterization of MOSFETs and their integrated circuits. We propose a simple "parasitic junction current method" (PJCM) for the separate extraction of R S , R D , and R SUB (substrate resistance) in MOSFETs. We applied the proposed PJCM to n-channel MOSFETs with different W / L combinations and verified its usefulness in the robust extraction of R S , R D , and R SUB .
ISSN:	0741-3106 1558-0563
DOI:	10.1109/LED.2010.2066257