A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS
A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s internally, all logic and testability functions could be im...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2010-10, Vol.45 (10), p.2016-2029 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 45 |
| creator | Nedovic, N Kristensson, A Parikh, S Reddy, S McLeod, S Tzartzanis, N Kanda, K Yamamoto, T Matsubara, S Kibune, M Doi, Y Ide, S Tsunoda, Y Yamabana, T Shibasaki, T Tomita, Y Hamada, T Sugawara, M Ikeuchi, T Kuwata, N Tamura, H Ogawa, J Walker, W |
| description | A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s internally, all logic and testability functions could be implemented in standard-cell CMOS, resulting in total power consumption of 3 W, 75 % lower than commercial BiCMOS SFI5 40 Gb/s SerDes ICs. Chip area is 4 × 4 mm, and the ICs are flip-chip mounted into a quad flat-pack package. |
| doi_str_mv | 10.1109/JSSC.2010.2057970 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_journals_1029868525</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5579985</ieee_id><sourcerecordid>855690921</sourcerecordid><originalsourceid>FETCH-LOGICAL-c355t-81e754d51d3c776971fda2ebd76f0f73371c87b6f410496d9d7abfe59d196edc3</originalsourceid><addsrcrecordid>eNpdkEtLw0AUhQdRsFZ_gLgZEHGVdB6581iW1NZKSxdRdBemmQmmpEnNpAv_vVNaunB17-F-53A5CN1TElNK9Ogty9KYkSAZAakluUADCqAiKvnXJRoQQlWkGSHX6Mb7TZBJougATceY40_T95jrWEVJEgs8W488nuxNHS1b63A2nUPMcOa6ifM4_a52Ye9x1WABuNnidLnKbtFVaWrv7k5ziD6mL-_pa7RYzebpeBEVHKCPFHUSEgvU8kJKoSUtrWFubaUoSSk5l7RQci3KhJJEC6utNOvSgbZUC2cLPkTPx9xd1_7sne_zbeULV9emce3e5wpAaKIZDeTjP3LT7rsmPJdTwrQSChgEih6pomu971yZ77pqa7rfAOWHYvNDsfmh2PxUbPA8nZKNL0xddqYpKn82Ms5EAkQE7uHIVc658xlCiFbA_wB46Xn_</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1029868525</pqid></control><display><type>article</type><title>A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS</title><source>IEEE Electronic Library (IEL)</source><creator>Nedovic, N ; Kristensson, A ; Parikh, S ; Reddy, S ; McLeod, S ; Tzartzanis, N ; Kanda, K ; Yamamoto, T ; Matsubara, S ; Kibune, M ; Doi, Y ; Ide, S ; Tsunoda, Y ; Yamabana, T ; Shibasaki, T ; Tomita, Y ; Hamada, T ; Sugawara, M ; Ikeuchi, T ; Kuwata, N ; Tamura, H ; Ogawa, J ; Walker, W</creator><creatorcontrib>Nedovic, N ; Kristensson, A ; Parikh, S ; Reddy, S ; McLeod, S ; Tzartzanis, N ; Kanda, K ; Yamamoto, T ; Matsubara, S ; Kibune, M ; Doi, Y ; Ide, S ; Tsunoda, Y ; Yamabana, T ; Shibasaki, T ; Tomita, Y ; Hamada, T ; Sugawara, M ; Ikeuchi, T ; Kuwata, N ; Tamura, H ; Ogawa, J ; Walker, W</creatorcontrib><description>A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s internally, all logic and testability functions could be implemented in standard-cell CMOS, resulting in total power consumption of 3 W, 75 % lower than commercial BiCMOS SFI5 40 Gb/s SerDes ICs. Chip area is 4 × 4 mm, and the ICs are flip-chip mounted into a quad flat-pack package.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2010.2057970</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Amplifiers ; Applied sciences ; Chips ; Circuit properties ; Circuits ; Circuits of signal characteristics conditioning (including delay circuits) ; clock data recovery (CDR) ; Clocks ; CMOS ; CMOS integrated circuits ; common-mode logic (CML) ; Delay ; Demultiplexing ; deserializer ; Design. Technologies. Operation analysis. Testing ; deskew ; DQPSK ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; Integrated circuits ; Limiting ; limiting amplifier ; Optical device fabrication ; optical transponder ; Oscillators, resonators, synthetizers ; Packages ; phase interpolator ; Phase locked loops ; phase-locked loop (PLL) ; Power consumption ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; SERD ; SerDes ; Serializer ; SFI5.2 ; Testability ; Transponders ; voltage-controlled oscillator (VCO)</subject><ispartof>IEEE journal of solid-state circuits, 2010-10, Vol.45 (10), p.2016-2029</ispartof><rights>2015 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Oct 2010</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c355t-81e754d51d3c776971fda2ebd76f0f73371c87b6f410496d9d7abfe59d196edc3</citedby><cites>FETCH-LOGICAL-c355t-81e754d51d3c776971fda2ebd76f0f73371c87b6f410496d9d7abfe59d196edc3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5579985$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,314,776,780,785,786,792,23909,23910,25118,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5579985$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=23264506$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Nedovic, N</creatorcontrib><creatorcontrib>Kristensson, A</creatorcontrib><creatorcontrib>Parikh, S</creatorcontrib><creatorcontrib>Reddy, S</creatorcontrib><creatorcontrib>McLeod, S</creatorcontrib><creatorcontrib>Tzartzanis, N</creatorcontrib><creatorcontrib>Kanda, K</creatorcontrib><creatorcontrib>Yamamoto, T</creatorcontrib><creatorcontrib>Matsubara, S</creatorcontrib><creatorcontrib>Kibune, M</creatorcontrib><creatorcontrib>Doi, Y</creatorcontrib><creatorcontrib>Ide, S</creatorcontrib><creatorcontrib>Tsunoda, Y</creatorcontrib><creatorcontrib>Yamabana, T</creatorcontrib><creatorcontrib>Shibasaki, T</creatorcontrib><creatorcontrib>Tomita, Y</creatorcontrib><creatorcontrib>Hamada, T</creatorcontrib><creatorcontrib>Sugawara, M</creatorcontrib><creatorcontrib>Ikeuchi, T</creatorcontrib><creatorcontrib>Kuwata, N</creatorcontrib><creatorcontrib>Tamura, H</creatorcontrib><creatorcontrib>Ogawa, J</creatorcontrib><creatorcontrib>Walker, W</creatorcontrib><title>A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s internally, all logic and testability functions could be implemented in standard-cell CMOS, resulting in total power consumption of 3 W, 75 % lower than commercial BiCMOS SFI5 40 Gb/s SerDes ICs. Chip area is 4 × 4 mm, and the ICs are flip-chip mounted into a quad flat-pack package.</description><subject>Amplifiers</subject><subject>Applied sciences</subject><subject>Chips</subject><subject>Circuit properties</subject><subject>Circuits</subject><subject>Circuits of signal characteristics conditioning (including delay circuits)</subject><subject>clock data recovery (CDR)</subject><subject>Clocks</subject><subject>CMOS</subject><subject>CMOS integrated circuits</subject><subject>common-mode logic (CML)</subject><subject>Delay</subject><subject>Demultiplexing</subject><subject>deserializer</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>deskew</subject><subject>DQPSK</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Limiting</subject><subject>limiting amplifier</subject><subject>Optical device fabrication</subject><subject>optical transponder</subject><subject>Oscillators, resonators, synthetizers</subject><subject>Packages</subject><subject>phase interpolator</subject><subject>Phase locked loops</subject><subject>phase-locked loop (PLL)</subject><subject>Power consumption</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>SERD</subject><subject>SerDes</subject><subject>Serializer</subject><subject>SFI5.2</subject><subject>Testability</subject><subject>Transponders</subject><subject>voltage-controlled oscillator (VCO)</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2010</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkEtLw0AUhQdRsFZ_gLgZEHGVdB6581iW1NZKSxdRdBemmQmmpEnNpAv_vVNaunB17-F-53A5CN1TElNK9Ogty9KYkSAZAakluUADCqAiKvnXJRoQQlWkGSHX6Mb7TZBJougATceY40_T95jrWEVJEgs8W488nuxNHS1b63A2nUPMcOa6ifM4_a52Ye9x1WABuNnidLnKbtFVaWrv7k5ziD6mL-_pa7RYzebpeBEVHKCPFHUSEgvU8kJKoSUtrWFubaUoSSk5l7RQci3KhJJEC6utNOvSgbZUC2cLPkTPx9xd1_7sne_zbeULV9emce3e5wpAaKIZDeTjP3LT7rsmPJdTwrQSChgEih6pomu971yZ77pqa7rfAOWHYvNDsfmh2PxUbPA8nZKNL0xddqYpKn82Ms5EAkQE7uHIVc658xlCiFbA_wB46Xn_</recordid><startdate>20101001</startdate><enddate>20101001</enddate><creator>Nedovic, N</creator><creator>Kristensson, A</creator><creator>Parikh, S</creator><creator>Reddy, S</creator><creator>McLeod, S</creator><creator>Tzartzanis, N</creator><creator>Kanda, K</creator><creator>Yamamoto, T</creator><creator>Matsubara, S</creator><creator>Kibune, M</creator><creator>Doi, Y</creator><creator>Ide, S</creator><creator>Tsunoda, Y</creator><creator>Yamabana, T</creator><creator>Shibasaki, T</creator><creator>Tomita, Y</creator><creator>Hamada, T</creator><creator>Sugawara, M</creator><creator>Ikeuchi, T</creator><creator>Kuwata, N</creator><creator>Tamura, H</creator><creator>Ogawa, J</creator><creator>Walker, W</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope><scope>KR7</scope></search><sort><creationdate>20101001</creationdate><title>A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS</title><author>Nedovic, N ; Kristensson, A ; Parikh, S ; Reddy, S ; McLeod, S ; Tzartzanis, N ; Kanda, K ; Yamamoto, T ; Matsubara, S ; Kibune, M ; Doi, Y ; Ide, S ; Tsunoda, Y ; Yamabana, T ; Shibasaki, T ; Tomita, Y ; Hamada, T ; Sugawara, M ; Ikeuchi, T ; Kuwata, N ; Tamura, H ; Ogawa, J ; Walker, W</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c355t-81e754d51d3c776971fda2ebd76f0f73371c87b6f410496d9d7abfe59d196edc3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Amplifiers</topic><topic>Applied sciences</topic><topic>Chips</topic><topic>Circuit properties</topic><topic>Circuits</topic><topic>Circuits of signal characteristics conditioning (including delay circuits)</topic><topic>clock data recovery (CDR)</topic><topic>Clocks</topic><topic>CMOS</topic><topic>CMOS integrated circuits</topic><topic>common-mode logic (CML)</topic><topic>Delay</topic><topic>Demultiplexing</topic><topic>deserializer</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>deskew</topic><topic>DQPSK</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Integrated circuits</topic><topic>Limiting</topic><topic>limiting amplifier</topic><topic>Optical device fabrication</topic><topic>optical transponder</topic><topic>Oscillators, resonators, synthetizers</topic><topic>Packages</topic><topic>phase interpolator</topic><topic>Phase locked loops</topic><topic>phase-locked loop (PLL)</topic><topic>Power consumption</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>SERD</topic><topic>SerDes</topic><topic>Serializer</topic><topic>SFI5.2</topic><topic>Testability</topic><topic>Transponders</topic><topic>voltage-controlled oscillator (VCO)</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Nedovic, N</creatorcontrib><creatorcontrib>Kristensson, A</creatorcontrib><creatorcontrib>Parikh, S</creatorcontrib><creatorcontrib>Reddy, S</creatorcontrib><creatorcontrib>McLeod, S</creatorcontrib><creatorcontrib>Tzartzanis, N</creatorcontrib><creatorcontrib>Kanda, K</creatorcontrib><creatorcontrib>Yamamoto, T</creatorcontrib><creatorcontrib>Matsubara, S</creatorcontrib><creatorcontrib>Kibune, M</creatorcontrib><creatorcontrib>Doi, Y</creatorcontrib><creatorcontrib>Ide, S</creatorcontrib><creatorcontrib>Tsunoda, Y</creatorcontrib><creatorcontrib>Yamabana, T</creatorcontrib><creatorcontrib>Shibasaki, T</creatorcontrib><creatorcontrib>Tomita, Y</creatorcontrib><creatorcontrib>Hamada, T</creatorcontrib><creatorcontrib>Sugawara, M</creatorcontrib><creatorcontrib>Ikeuchi, T</creatorcontrib><creatorcontrib>Kuwata, N</creatorcontrib><creatorcontrib>Tamura, H</creatorcontrib><creatorcontrib>Ogawa, J</creatorcontrib><creatorcontrib>Walker, W</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Civil Engineering Abstracts</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nedovic, N</au><au>Kristensson, A</au><au>Parikh, S</au><au>Reddy, S</au><au>McLeod, S</au><au>Tzartzanis, N</au><au>Kanda, K</au><au>Yamamoto, T</au><au>Matsubara, S</au><au>Kibune, M</au><au>Doi, Y</au><au>Ide, S</au><au>Tsunoda, Y</au><au>Yamabana, T</au><au>Shibasaki, T</au><au>Tomita, Y</au><au>Hamada, T</au><au>Sugawara, M</au><au>Ikeuchi, T</au><au>Kuwata, N</au><au>Tamura, H</au><au>Ogawa, J</au><au>Walker, W</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2010-10-01</date><risdate>2010</risdate><volume>45</volume><issue>10</issue><spage>2016</spage><epage>2029</epage><pages>2016-2029</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s internally, all logic and testability functions could be implemented in standard-cell CMOS, resulting in total power consumption of 3 W, 75 % lower than commercial BiCMOS SFI5 40 Gb/s SerDes ICs. Chip area is 4 × 4 mm, and the ICs are flip-chip mounted into a quad flat-pack package.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/JSSC.2010.2057970</doi><tpages>14</tpages></addata></record> |
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| subjects | Amplifiers Applied sciences Chips Circuit properties Circuits Circuits of signal characteristics conditioning (including delay circuits) clock data recovery (CDR) Clocks CMOS CMOS integrated circuits common-mode logic (CML) Delay Demultiplexing deserializer Design. Technologies. Operation analysis. Testing deskew DQPSK Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Integrated circuits Limiting limiting amplifier Optical device fabrication optical transponder Oscillators, resonators, synthetizers Packages phase interpolator Phase locked loops phase-locked loop (PLL) Power consumption Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices SERD SerDes Serializer SFI5.2 Testability Transponders voltage-controlled oscillator (VCO) |
| title | A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-05T13%3A11%3A40IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%203%20Watt%2039.8-44.6%20Gb/s%20Dual-Mode%20SFI5.2%20SerDes%20Chip%20Set%20in%2065%20nm%20CMOS&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Nedovic,%20N&rft.date=2010-10-01&rft.volume=45&rft.issue=10&rft.spage=2016&rft.epage=2029&rft.pages=2016-2029&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/JSSC.2010.2057970&rft_dat=%3Cproquest_RIE%3E855690921%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=1029868525&rft_id=info:pmid/&rft_ieee_id=5579985&rfr_iscdi=true |