A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS

A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s internally, all logic and testability functions could be im...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2010-10, Vol.45 (10), p.2016-2029
Hauptverfasser:	Nedovic, N, Kristensson, A, Parikh, S, Reddy, S, McLeod, S, Tzartzanis, N, Kanda, K, Yamamoto, T, Matsubara, S, Kibune, M, Doi, Y, Ide, S, Tsunoda, Y, Yamabana, T, Shibasaki, T, Tomita, Y, Hamada, T, Sugawara, M, Ikeuchi, T, Kuwata, N, Tamura, H, Ogawa, J, Walker, W
Format:	Artikel
Sprache:	eng
Schlagworte:	Amplifiers Applied sciences Chips Circuit properties Circuits Circuits of signal characteristics conditioning (including delay circuits) clock data recovery (CDR) Clocks CMOS CMOS integrated circuits common-mode logic (CML) Delay Demultiplexing deserializer Design. Technologies. Operation analysis. Testing deskew DQPSK Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Integrated circuits Limiting limiting amplifier Optical device fabrication optical transponder Oscillators, resonators, synthetizers Packages phase interpolator Phase locked loops phase-locked loop (PLL) Power consumption Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices SERD SerDes Serializer SFI5.2 Testability Transponders voltage-controlled oscillator (VCO)
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Zusammenfassung:	A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s internally, all logic and testability functions could be implemented in standard-cell CMOS, resulting in total power consumption of 3 W, 75 % lower than commercial BiCMOS SFI5 40 Gb/s SerDes ICs. Chip area is 4 × 4 mm, and the ICs are flip-chip mounted into a quad flat-pack package.
ISSN:	0018-9200 1558-173X
DOI:	10.1109/JSSC.2010.2057970