Effective Surface Passivation by Novel [Formula Omitted]-[Formula Omitted] Treatment and BTI Characteristics on Interface-Engineered High-Mobility [Formula Omitted]-Gated Ge pMOSFETs
A novel surface passivation technique using silicon nitride (SN) by [Formula Omitted]-[Formula Omitted] treatment has been demonstrated on [Formula Omitted]-gated Ge pMOSFETs. It is found that ultrathin SN passivation is more effective to suppress the Ge out diffusion than ultrathin Si passivation....
Gespeichert in:
Veröffentlicht in: | IEEE transactions on electron devices 2010-06, Vol.57 (6), p.1399 |
---|---|
Hauptverfasser: | , , , |
Format: | Artikel |
Sprache: | eng |
Online-Zugang: | Volltext |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | 6 |
container_start_page | 1399 |
container_title | IEEE transactions on electron devices |
container_volume | 57 |
creator | Xie, Ruilong Phung, Thanh Hoa Yu, Mingbin Zhu, Chunxiang |
description | A novel surface passivation technique using silicon nitride (SN) by [Formula Omitted]-[Formula Omitted] treatment has been demonstrated on [Formula Omitted]-gated Ge pMOSFETs. It is found that ultrathin SN passivation is more effective to suppress the Ge out diffusion than ultrathin Si passivation. Improved interface quality and device performance were achieved for the device with the SN passivation. Fluorine (F) incorporation by postgate treatment was also implemented to further enhance the performance. Furthermore, bias temperature instability (BTI) characteristics were systematically investigated on interface engineered (Si-, SN-, or [Formula Omitted]-passivated) Ge pMOSFETs by both conventional dc [Formula Omitted]-[Formula Omitted] and fast pulse measurement. The impact of [Formula Omitted] thickness and postgate treatment processes (F incorporation) on BTI and device performance was also studied, and it is found that BTI and device performance can be improved by reducing the [Formula Omitted] thickness or incorporating F. |
doi_str_mv | 10.1109/TED.2010.2046992 |
format | Article |
fullrecord | <record><control><sourceid>proquest</sourceid><recordid>TN_cdi_proquest_journals_1027190106</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>2716840841</sourcerecordid><originalsourceid>FETCH-proquest_journals_10271901063</originalsourceid><addsrcrecordid>eNqNkEtPwzAQhC0EEuFx57gSZxc7SdP6Skkfh1Kk5oZQ5Sab1lViF9uJ1D_G76uRuMGB0-ibXc1IQ8gDZwPOmXgq8pdBzALFLM2EiC9IxIfDERVZml2SiDE-piIZJ9fkxrlDwCxN44h85XWNpVc9wrqztSwR3qRzqpdeGQ3bE7yaHht4nxrbdo2EVau8x-qD_nKgsCh9i9qD1BU8FwuY7KWVpUernFelg5C40AG_e2iud0ojWqxgrnZ7ujRb1Sh_-qNrJoPADOG4XK2neeHuyFUtG4f3P3pLHoM9mdOjNZ8dOr85mM7qcNpwFo-4CMtkyf--zmT-agU</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1027190106</pqid></control><display><type>article</type><title>Effective Surface Passivation by Novel [Formula Omitted]-[Formula Omitted] Treatment and BTI Characteristics on Interface-Engineered High-Mobility [Formula Omitted]-Gated Ge pMOSFETs</title><source>IEEE Electronic Library (IEL)</source><creator>Xie, Ruilong ; Phung, Thanh Hoa ; Yu, Mingbin ; Zhu, Chunxiang</creator><creatorcontrib>Xie, Ruilong ; Phung, Thanh Hoa ; Yu, Mingbin ; Zhu, Chunxiang</creatorcontrib><description>A novel surface passivation technique using silicon nitride (SN) by [Formula Omitted]-[Formula Omitted] treatment has been demonstrated on [Formula Omitted]-gated Ge pMOSFETs. It is found that ultrathin SN passivation is more effective to suppress the Ge out diffusion than ultrathin Si passivation. Improved interface quality and device performance were achieved for the device with the SN passivation. Fluorine (F) incorporation by postgate treatment was also implemented to further enhance the performance. Furthermore, bias temperature instability (BTI) characteristics were systematically investigated on interface engineered (Si-, SN-, or [Formula Omitted]-passivated) Ge pMOSFETs by both conventional dc [Formula Omitted]-[Formula Omitted] and fast pulse measurement. The impact of [Formula Omitted] thickness and postgate treatment processes (F incorporation) on BTI and device performance was also studied, and it is found that BTI and device performance can be improved by reducing the [Formula Omitted] thickness or incorporating F.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2010.2046992</identifier><language>eng</language><publisher>New York: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</publisher><ispartof>IEEE transactions on electron devices, 2010-06, Vol.57 (6), p.1399</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Jun 2010</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,778,782,27911,27912</link.rule.ids></links><search><creatorcontrib>Xie, Ruilong</creatorcontrib><creatorcontrib>Phung, Thanh Hoa</creatorcontrib><creatorcontrib>Yu, Mingbin</creatorcontrib><creatorcontrib>Zhu, Chunxiang</creatorcontrib><title>Effective Surface Passivation by Novel [Formula Omitted]-[Formula Omitted] Treatment and BTI Characteristics on Interface-Engineered High-Mobility [Formula Omitted]-Gated Ge pMOSFETs</title><title>IEEE transactions on electron devices</title><description>A novel surface passivation technique using silicon nitride (SN) by [Formula Omitted]-[Formula Omitted] treatment has been demonstrated on [Formula Omitted]-gated Ge pMOSFETs. It is found that ultrathin SN passivation is more effective to suppress the Ge out diffusion than ultrathin Si passivation. Improved interface quality and device performance were achieved for the device with the SN passivation. Fluorine (F) incorporation by postgate treatment was also implemented to further enhance the performance. Furthermore, bias temperature instability (BTI) characteristics were systematically investigated on interface engineered (Si-, SN-, or [Formula Omitted]-passivated) Ge pMOSFETs by both conventional dc [Formula Omitted]-[Formula Omitted] and fast pulse measurement. The impact of [Formula Omitted] thickness and postgate treatment processes (F incorporation) on BTI and device performance was also studied, and it is found that BTI and device performance can be improved by reducing the [Formula Omitted] thickness or incorporating F.</description><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2010</creationdate><recordtype>article</recordtype><recordid>eNqNkEtPwzAQhC0EEuFx57gSZxc7SdP6Skkfh1Kk5oZQ5Sab1lViF9uJ1D_G76uRuMGB0-ibXc1IQ8gDZwPOmXgq8pdBzALFLM2EiC9IxIfDERVZml2SiDE-piIZJ9fkxrlDwCxN44h85XWNpVc9wrqztSwR3qRzqpdeGQ3bE7yaHht4nxrbdo2EVau8x-qD_nKgsCh9i9qD1BU8FwuY7KWVpUernFelg5C40AG_e2iud0ojWqxgrnZ7ujRb1Sh_-qNrJoPADOG4XK2neeHuyFUtG4f3P3pLHoM9mdOjNZ8dOr85mM7qcNpwFo-4CMtkyf--zmT-agU</recordid><startdate>20100601</startdate><enddate>20100601</enddate><creator>Xie, Ruilong</creator><creator>Phung, Thanh Hoa</creator><creator>Yu, Mingbin</creator><creator>Zhu, Chunxiang</creator><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>20100601</creationdate><title>Effective Surface Passivation by Novel [Formula Omitted]-[Formula Omitted] Treatment and BTI Characteristics on Interface-Engineered High-Mobility [Formula Omitted]-Gated Ge pMOSFETs</title><author>Xie, Ruilong ; Phung, Thanh Hoa ; Yu, Mingbin ; Zhu, Chunxiang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-proquest_journals_10271901063</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2010</creationdate><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Xie, Ruilong</creatorcontrib><creatorcontrib>Phung, Thanh Hoa</creatorcontrib><creatorcontrib>Yu, Mingbin</creatorcontrib><creatorcontrib>Zhu, Chunxiang</creatorcontrib><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Xie, Ruilong</au><au>Phung, Thanh Hoa</au><au>Yu, Mingbin</au><au>Zhu, Chunxiang</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Effective Surface Passivation by Novel [Formula Omitted]-[Formula Omitted] Treatment and BTI Characteristics on Interface-Engineered High-Mobility [Formula Omitted]-Gated Ge pMOSFETs</atitle><jtitle>IEEE transactions on electron devices</jtitle><date>2010-06-01</date><risdate>2010</risdate><volume>57</volume><issue>6</issue><spage>1399</spage><pages>1399-</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><abstract>A novel surface passivation technique using silicon nitride (SN) by [Formula Omitted]-[Formula Omitted] treatment has been demonstrated on [Formula Omitted]-gated Ge pMOSFETs. It is found that ultrathin SN passivation is more effective to suppress the Ge out diffusion than ultrathin Si passivation. Improved interface quality and device performance were achieved for the device with the SN passivation. Fluorine (F) incorporation by postgate treatment was also implemented to further enhance the performance. Furthermore, bias temperature instability (BTI) characteristics were systematically investigated on interface engineered (Si-, SN-, or [Formula Omitted]-passivated) Ge pMOSFETs by both conventional dc [Formula Omitted]-[Formula Omitted] and fast pulse measurement. The impact of [Formula Omitted] thickness and postgate treatment processes (F incorporation) on BTI and device performance was also studied, and it is found that BTI and device performance can be improved by reducing the [Formula Omitted] thickness or incorporating F.</abstract><cop>New York</cop><pub>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</pub><doi>10.1109/TED.2010.2046992</doi></addata></record> |
fulltext | fulltext |
identifier | ISSN: 0018-9383 |
ispartof | IEEE transactions on electron devices, 2010-06, Vol.57 (6), p.1399 |
issn | 0018-9383 1557-9646 |
language | eng |
recordid | cdi_proquest_journals_1027190106 |
source | IEEE Electronic Library (IEL) |
title | Effective Surface Passivation by Novel [Formula Omitted]-[Formula Omitted] Treatment and BTI Characteristics on Interface-Engineered High-Mobility [Formula Omitted]-Gated Ge pMOSFETs |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-15T23%3A54%3A15IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Effective%20Surface%20Passivation%20by%20Novel%20%5BFormula%20Omitted%5D-%5BFormula%20Omitted%5D%20Treatment%20and%20BTI%20Characteristics%20on%20Interface-Engineered%20High-Mobility%20%5BFormula%20Omitted%5D-Gated%20Ge%20pMOSFETs&rft.jtitle=IEEE%20transactions%20on%20electron%20devices&rft.au=Xie,%20Ruilong&rft.date=2010-06-01&rft.volume=57&rft.issue=6&rft.spage=1399&rft.pages=1399-&rft.issn=0018-9383&rft.eissn=1557-9646&rft_id=info:doi/10.1109/TED.2010.2046992&rft_dat=%3Cproquest%3E2716840841%3C/proquest%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=1027190106&rft_id=info:pmid/&rfr_iscdi=true |