A Practical Model Assessing the Degradation of Polycrystalline Silicon TFTs Due to DC Electrical Stress

Degradation phenomena under the application of a variety of hot-carrier stress conditions were investigated in n-channel top-gate polysilicon thin-film transistors of various channel widths, fabricated by sequential lateral solidification excimer laser annealing. A simple and practical model was developed in order to predict the dc-stress-induced degradation and the evolution during stress of the critical electrical parameters of device performance, such as the threshold voltage. The presented model suggests a series combination of a defective and a nondefective region of the device's channel. It was found that the spreading of the damaged region along the channel from the drain toward the source is width dependent. In order to investigate that, devices with different channel widths were compared. By extracting and monitoring the electrical parameters in the linear regime of operation, after each stress cycle, the fitted results of the model were compared and evaluated.