A 32-bit VLSI digital signal processor

A general-purpose programmable digital signal processor (DSP) has been implemented in 1.5-/spl mu/m (L/SUB eff/) NMOS technology using full-custom circuit design for high performance. The DSP has a 32-bit instruction set, 32-bit data path, and full-hardware 32-bit floating-point arithmetic. The arch...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1985-10, Vol.20 (5), p.998-1004
Hauptverfasser:	Hayes, W.P., Kershaw, R.N., Bays, L.E., Boddie, J.R., Fields, E.M., Freyman, R.L., Garen, C.J., Hartung, J., Klinikowski, J.J., Miller, C.R., Mondal, K., Moscovitz, H.S., Rotblum, Y., Stocker, W.A., Tow, J., Tran, L.V.
Format:	Artikel
Sprache:	eng
Schlagworte:	Application software Applied sciences Circuit properties Circuit synthesis Digital circuits Digital signal processing Digital signal processors Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Filters Floating-point arithmetic MOS devices Process design Registers Very large scale integration
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Beschreibung
Zusammenfassung:	A general-purpose programmable digital signal processor (DSP) has been implemented in 1.5-/spl mu/m (L/SUB eff/) NMOS technology using full-custom circuit design for high performance. The DSP has a 32-bit instruction set, 32-bit data path, and full-hardware 32-bit floating-point arithmetic. The architecture is described section by section, and an overview of the instruction set is presented. The extensive design verification process applied to the DSP is also described.
ISSN:	0018-9200 1558-173X
DOI:	10.1109/JSSC.1985.1052427