REDUSA: module generation by automatic elimination of superfluous blocks in regular structures
An approach to module generation that does not require the construction of parametrized software procedures is presented. It is a design-by-example method that is based on the following concept: an example module (e.g., a 16-b multiplier) realizes a function between the set of input combinations and...
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| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 1989-09, Vol.8 (9), p.989-998 |
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| container_issue | 9 |
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| container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
| container_volume | 8 |
| creator | Vandeweerd, I. Croes, K. Rijnders, L. Six, P. De Man, H.J. |
| description | An approach to module generation that does not require the construction of parametrized software procedures is presented. It is a design-by-example method that is based on the following concept: an example module (e.g., a 16-b multiplier) realizes a function between the set of input combinations and the set of output combinations. In many applications, only a subset of input combinations (e.g., 8-b instead of 16-b inputs) is used. The restriction of the module's function to this subset can be realized by a simpler module. REDUSA constructs this module automatically by a reduction of the example module. This approach offers important advantages in both the construction and verification aspected of module generators.< > |
| doi_str_mv | 10.1109/43.35551 |
| format | Article |
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Testing</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Logic design</subject><subject>Modular construction</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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| identifier | ISSN: 0278-0070 |
| ispartof | IEEE transactions on computer-aided design of integrated circuits and systems, 1989-09, Vol.8 (9), p.989-998 |
| issn | 0278-0070 1937-4151 |
| language | eng |
| recordid | cdi_pascalfrancis_primary_7357994 |
| source | IEEE Electronic Library (IEL) |
| subjects | Application software Applied sciences Arithmetic Design automation Design methodology Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Integrated circuits Logic design Modular construction Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Software debugging Software libraries Software maintenance Software tools |
| title | REDUSA: module generation by automatic elimination of superfluous blocks in regular structures |
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