Integer multiplication and division on the HP Precision Architecture

Integer multiplication and division on the HP Precision Architecture

In recent years, many architectural design efforts have focused on maximizing performance for frequently executed, simple instructions. The authors describe how a small set of primitive instructions combined with what is considered careful frequency analysis and clever programming allows the Hewlett...

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Veröffentlicht in:IEEE transactions on computers 1988-08, Vol.37 (8), p.980-990
Hauptverfasser: Magenheimer, D.J., Peters, L., Pettis, K.W., Zuras, D.
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Arithmetic
Computer aided instruction
Computer architecture
Computer science
control theory
systems
Costs
Encoding
Exact sciences and technology
Frequency conversion
Hardware
High level languages
Language processing and microprogramming
Performance analysis
Reduced instruction set computing
Software
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Beschreibung
Zusammenfassung:In recent years, many architectural design efforts have focused on maximizing performance for frequently executed, simple instructions. The authors describe how a small set of primitive instructions combined with what is considered careful frequency analysis and clever programming allows the Hewlett-Packard (HP) Precision Architecture integer multiplication and division implementation to provide adequate performance at little or no hardware cost.< >
ISSN:0018-9340
1557-9956
DOI:10.1109/12.2248