Sub-300-ps CBL circuits

Sub-300-ps CBL circuits

Advanced charge-buffered-logic (CBL) circuits featuring double-poly self-alignment, a 'free' epi-base lateral p-n-p (cutoff frequency=300 MHz only), and deep trench isolation are discussed. Using 1.2- mu m design rules and a modified push-pull output stage, a gate delay (fan-in=3) of 278 p...

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Veröffentlicht in:IEEE electron device letters 1989-11, Vol.10 (11), p.484-486
Hauptverfasser: Widemann, S.K., Chen, T.-C., Chuang, C.-T., Heuber, K., Wendel, D.F., Warnock, J., Li, G.P., Chin, K., Ning, T.H.
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Buffer storage
Circuits
Cutoff frequency
Delay
Diodes
Electronics
Exact sciences and technology
Integrated circuits
Integrated circuits by function (including memories and processors)
Isolation technology
Logic devices
MOSFETs
Power dissipation
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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Beschreibung
Zusammenfassung:Advanced charge-buffered-logic (CBL) circuits featuring double-poly self-alignment, a 'free' epi-base lateral p-n-p (cutoff frequency=300 MHz only), and deep trench isolation are discussed. Using 1.2- mu m design rules and a modified push-pull output stage, a gate delay (fan-in=3) of 278 ps was obtained at a DC current of 30 mu A/gate. The low power-delay product underlies the speed and power potential of CBL as an attractive practical approach to bipolar complementary transistor logic.< >
ISSN:0741-3106
1558-0563
DOI:10.1109/55.43111