Strain-gauge mapping of die surface stresses

The distribution of die surface stresses in integrated circuits has been determined experimentally using a specially designed semiconductor-strain-gauge array. Specifically, 28-pin dual-in-line packages were assembled with different molding compounds and subjected to thermal shock testing. To monitor changes in the mechanical integrity of the package, surface stress from the samples were plotted along various die symmetry axes. These profiles show that principal stresses are highest at the center of the die, while maximum in-plane shear stresses are highest at the corners. The principal stress levels at the center of the die are useful in comparing different molding compound formulations, while maximum shear stresses are useful in evaluating changes in mechanical integrity due to accelerated life testing.< >