Potential distribution and interface states in the input stage of an amorphous silicon thin-film transistor

Some properties of the input stage of an amorphous Si (a-Si) thin-film transistor have been studied on an analogous large-area a-Si-a-SiN structure which mimicked the overlap region between source and gate in a real device. Audio-frequency capacitance-voltage techniques were used between 170 and 380 K to deduce internal parameters of the system. When the gate was positively biased, thick a-Si layers were found to lead to an internal barrier whose properties could be reliably quantified using capacitance and equivalent series resistance measurements. Studies of the parallel conductance of the devices showed that, for a forward gate bias, significant losses resulting from charge injected into the nitride gate insulator could be detected whereas, for a reverse bias, loss associated with states at the a-Si-a-SiN interface was observed. Most unusually, this loss had an activated temperature dependence. The most likely mechanism to account for this loss is charging of interface states by tunnelling. A novel relaxation model is introduced to describe such a process, which is in reasonable agreement with the experimental data.