Sequential faults and aliasing

Aliasing is studied for delay and stuck-open faults. It is shown that, as the test sequence length is increased, the probability of aliasing for such faults tend to 2/sup -k/, where k is the number of binary memory elements in a linear compactor. The result is based on the assumption that the linear...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 1993-07, Vol.12 (7), p.1068-1074
Hauptverfasser:	Pilarski, S., Kameda, T., Ivanov, A.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Automatic testing Built-in self-test Circuit faults Circuit testing Compaction Delay Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Fault detection Integrated circuits Registers Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Sequential circuits Very large scale integration
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	Aliasing is studied for delay and stuck-open faults. It is shown that, as the test sequence length is increased, the probability of aliasing for such faults tend to 2/sup -k/, where k is the number of binary memory elements in a linear compactor. The result is based on the assumption that the linear compactor has an irreducible characteristic polynomial. Some recent results on combinational faults are special cases of the results presented here.< >
ISSN:	0278-0070 1937-4151
DOI:	10.1109/43.238044