A comprehensive delay model for CMOS inverters

A method to accurately calculate the delay and the output transition-time of a CMOS inverter for any input ramp and output loading is considered. This paper is an extension of Sakurai's work (1990) on delay modeling of inverters for fast input ramps. We observed that two different mechanisms, that can be adequately modeled analytically, govern the delay and the output transition-time of an inverter in two extreme cases: infinitely fast and infinitely slow inputs. These extreme points are joined by a curve that can predict the delay and the output transition-time for any input. We found that the delay and the output transition-time for an inverter with small fanouts are similar to those for large input transition-times. This behavior is explained by the use of I-V trajectories. We describe a method to generate parameters to model delay and output transition-time for different fanouts and input transition-times; this method can be generalized to add parameters for different temperatures and supply voltages. Given a new process technology and its corresponding SPICE-model parameters, our delay calculation scheme comprises characterizing a minimal number of coefficients for each new technology (a one-time process) and evaluating the analytical forms thereafter to obtain the delay and the transition-time. Our delay equations also explain negative delays that arise in case of slow input rise-times. A program incorporating the above idea has been implemented in C. Delay and transition-time values obtained from the program have been found to be typically within 3% of SPICE.< >