Efficiency and reliability of Fowler-Nordheim tunnelling in CMOS floating-gate transistors

Floating-gate transistors are increasingly used for digital and/or analogue non-volatile memory in standard CMOS integrated circuits. The mask design of the floating-gate's tunnelling junction, where erasure and/or writing occur, is examined. Aided by static and transient tunnelling current measurements for a variety of tunnelling junctions, recommendations for constructing these junctions to minimise the duration, power consumption and oxide degradation of programming are presented.