A 10-b 1-GHz 33-mW CMOS ADC

This paper describes a pipelined analog-to-digital converter that resolves 4 b in its first stage and amplifies the residue by a factor of 2, thereby relaxing the opamp linearity, voltage swing, and gain requirements. Calibration in the digital domain removes the effect of capacitor mismatches and c...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2013-06, Vol.48 (6), p.1442-1452
Hauptverfasser:	Sahoo, B. D., Razavi, B.
Format:	Artikel
Sprache:	eng
Schlagworte:	Amplifiers Analog-to-digital converter (ADC) Applied sciences Calibration Capacitance Capacitors Circuit properties CMOS integrated circuits Design. Technologies. Operation analysis. Testing Dielectric, amorphous and glass solid devices Electric, optical and optoelectronic circuits Electronic circuits Electronics Equations Exact sciences and technology Gain gain error calibration Integrated circuits low power low-gain opamp multibit capacitor mismatch calibration Noise pipelined ADC Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal convertors
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Beschreibung
Zusammenfassung:	This paper describes a pipelined analog-to-digital converter that resolves 4 b in its first stage and amplifies the residue by a factor of 2, thereby relaxing the opamp linearity, voltage swing, and gain requirements. Calibration in the digital domain removes the effect of capacitor mismatches and corrects for the gain error. Using a one-stage opamp with a gain of 10 and realized in 65-nm CMOS technology, the ADC digitizes a 490-MHz input with a signal-to-(noise+distortion) ratio of 52.4 dB, achieving a figure of merit of 97 fJ/conversion-step.
ISSN:	0018-9200 1558-173X
DOI:	10.1109/JSSC.2013.2252518