A Cascode Feedback Bias Technique for Linear CMOS Power Amplifiers in a Multistage Cascode Topology

A novel feedback bias technique for a multistage cascode topology is developed to improve the linearity and reliability of power amplifiers (PAs). Due to the large parasitic capacitance and low substrate resistivity of CMOS technology, signal swings are coupled between the ports of transistors. The proposed method utilized the RF leakage signals at the gate of common-gate (CG) transistor in a cascode topology for employing negative feedback, which not only enhances the linearity of the PA, but also alleviates the voltage stress between the gate and the drain of the CG device in a cascode topology from 4.5 to 1.9 V. This technique requires no additional components or space and is easily applicable to the multistage cascode topology, which is one of the most popular structures of CMOS PA designs. In order to prove the concept, a 1.95-GHz fully integrated linear PA was implemented in a 0.18- μm CMOS technology. With a 3.4-V power supply, the PA transmits a saturated output power of 26 dBm with a power-added efficiency (PAE) of 46.4%, and a linear output power of 23.5 dBm with a PAE of 40% using a 3 GPP WCDMA modulated signal. The PA occupies 1.60 × 0.52 mm 2 . This PA demonstrates the potential of the highly efficient CMOS PA design approach for wireless communication standards.