Highly Linear Noise-Shaped Pipelined ADC Utilizing a Relaxed Accuracy Front-End

Highly Linear Noise-Shaped Pipelined ADC Utilizing a Relaxed Accuracy Front-End

A noise-shaped pipelined ADC is presented in this paper. A minimal complexity ΔΣ modulator in the first two sub-ADCs and residue feedback in the latter stages lead to high-order noise shaping. This also leads to reduced sensitivity to analog imperfections in the front-end stage. Implemented in 0.18-...

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Veröffentlicht in:IEEE journal of solid-state circuits 2013-02, Vol.48 (2), p.502-515
Hauptverfasser: Rajaee, O., Un-Ku Moon
Format: Artikel
Sprache:eng
Schlagworte:
Accuracy
Applied sciences
Circuit properties
Delta \Sigma modulation
Design. Technologies. Operation analysis. Testing
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
feedback DAC
Finite impulse response filter
Gain
Hardware
Input-output equipment
Integrated circuits
loop filter
Modulation
Noise
Noise shaping
oversampling converters
pipelined ADCs
Quantization
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal convertors
switched-capacitor circuits
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Zusammenfassung:A noise-shaped pipelined ADC is presented in this paper. A minimal complexity ΔΣ modulator in the first two sub-ADCs and residue feedback in the latter stages lead to high-order noise shaping. This also leads to reduced sensitivity to analog imperfections in the front-end stage. Implemented in 0.18- μm CMOS, the ADC achieves 12 ENOB with 64-MHz clock at 6× OSR while using only a 9-b linear front-end multiplying DAC. The delta-sigma sub-ADCs dissipate 400 μW of extra power (out of 13.9-mW total power) while significantly enhancing the overall ADC linearity.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2012.2227605