Using Cacheline Reuse Characteristics for Prefetcher Throttling : Parallel and Distributed Computing and Networking

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Veröffentlicht in:	IEICE transactions on information and systems 2012, Vol.95 (12), p.2928-2938
Hauptverfasser:	IRIE, Hidetsugu, MIYOSHI, Takefumi, HONJO, Goki, HIRAKI, Kei, YOSHINAGA, Tsutomu
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Computer science control theory systems Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Memory and file management (including protection and security) Memory organisation. Data processing Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Software
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ISSN:	0916-8532 1745-1361