A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme : Solid-State Circuit Design -Architecture, Circuit, Device and Design Methodology
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| Veröffentlicht in: | IEICE transactions on electronics 2012, Vol.95 (4), p.572-578 |
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| container_title | IEICE transactions on electronics |
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| creator | YOSHIMOTO, Shusuke TERADA, Masaharu OKUMURA, Shunsuke SUZUKI, Toshikazu MIYANO, Shinji KAWAGUCHI, Hiroshi YOSHIMOTO, Masahiko |
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| fulltext | fulltext |
| identifier | ISSN: 0916-8524 |
| ispartof | IEICE transactions on electronics, 2012, Vol.95 (4), p.572-578 |
| issn | 0916-8524 1745-1353 |
| language | eng |
| recordid | cdi_pascalfrancis_primary_25778784 |
| source | J-STAGE Free |
| subjects | Applied sciences Circuit properties Circuits of signal characteristics conditioning (including delay circuits) Design. Technologies. Operation analysis. Testing Electric, optical and optoelectronic circuits Electronic circuits Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices |
| title | A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme : Solid-State Circuit Design -Architecture, Circuit, Device and Design Methodology |
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