A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme : Solid-State Circuit Design -Architecture, Circuit, Device and Design Methodology

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme : Solid-State Circuit Design -Architecture, Circuit, Device and Design Methodology

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Bibliographische Detailangaben
Veröffentlicht in:IEICE transactions on electronics 2012, Vol.95 (4), p.572-578
Hauptverfasser: YOSHIMOTO, Shusuke, TERADA, Masaharu, OKUMURA, Shunsuke, SUZUKI, Toshikazu, MIYANO, Shinji, KAWAGUCHI, Hiroshi, YOSHIMOTO, Masahiko
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Circuit properties
Circuits of signal characteristics conditioning (including delay circuits)
Design. Technologies. Operation analysis. Testing
Electric, optical and optoelectronic circuits
Electronic circuits
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Exact sciences and technology
Integrated circuits
Integrated circuits by function (including memories and processors)
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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ISSN:0916-8524
1745-1353