Vertical-Gate Si/SiGe Double-HBT-Based Capacitorless IT DRAM Cell for Extended Retention Time at Low Latch Voltage
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| Veröffentlicht in: | IEEE electron device letters 2012, Vol.33 (2), p.134-136 |
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| container_end_page | 136 |
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| container_issue | 2 |
| container_start_page | 134 |
| container_title | IEEE electron device letters |
| container_volume | 33 |
| creator | JA SUN SHIN CHOI, Hyunjun BAE, Hagyoul JANG, Jaeman YUN, Daeyoun HONG, Euiyoun DAE HWAN KIM DONG MYONG KIM |
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| fulltext | fulltext |
| identifier | ISSN: 0741-3106 |
| ispartof | IEEE electron device letters, 2012, Vol.33 (2), p.134-136 |
| issn | 0741-3106 1558-0563 |
| language | eng |
| recordid | cdi_pascalfrancis_primary_25488335 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Compound structure devices Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Transistors |
| title | Vertical-Gate Si/SiGe Double-HBT-Based Capacitorless IT DRAM Cell for Extended Retention Time at Low Latch Voltage |
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