Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System

This paper describes the circuit and physical design features of the z196 processor chip, implemented in a 45 nm SOI technology. The chip contains 4 super-scalar, out-of-order processor cores, running at 5.2 GHz, on a die with an area of 512 mm 2 containing an estimated 1.4 billion transistors. The...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2012-01, Vol.47 (1), p.151-163
Hauptverfasser:	Warnock, J., Yiu-Hing Chan, Carey, S., Huajun Wen, Meaney, P., Gerwig, G., Smith, H. H., Yuen Chan, Davis, J., Bunce, P., Pelella, A., Rodko, D., Patel, P., Strach, T., Malone, D., Malgioglio, F., Neves, J., Rude, D. L., Huott, W.
Format:	Artikel
Sprache:	eng
Schlagworte:	45 nm SOI Applied sciences Arrays Cache set predict chip integration chip IR drop chip supply noise circuit design methodology clock distribution clock grid Clocks CMOS digital integrated circuits design for reliability design for test Design. Technologies. Operation analysis. Testing digital circuits Electronics Exact sciences and technology high-frequency CMOS design Integrated circuits Integrated circuits by function (including memories and processors) Logic gates microprocessor test microprocessors power efficiency RAIM Random access memory RAS reliability Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices SRAM system z Testing, measurement, noise and reliability Timing Transistors Tuning VLSI design Wires z196 zEnterprise zEnterprise 196
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Zusammenfassung:	This paper describes the circuit and physical design features of the z196 processor chip, implemented in a 45 nm SOI technology. The chip contains 4 super-scalar, out-of-order processor cores, running at 5.2 GHz, on a die with an area of 512 mm 2 containing an estimated 1.4 billion transistors. The core and chip design methodology and specific design features are presented, focusing on techniques used to enable high-frequency operation. In addition, chip power, IR drop, and supply noise are discussed, being key design focus areas. The chip's ground-breaking RAS features are also described, engineered for maximum reliability and system stability.
ISSN:	0018-9200 1558-173X
DOI:	10.1109/JSSC.2011.2169308