ORION 2.0: A Power-Area Simulator for Interconnection Networks

ORION 2.0: A Power-Area Simulator for Interconnection Networks

As industry moves towards multicore chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power has become crucially important. In this work, we present ORION 2.0, an enhanced...

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Veröffentlicht in:IEEE transactions on very large scale integration (VLSI) systems 2012-01, Vol.20 (1), p.191-196
Hauptverfasser: Kahng, A. B., Bin Li, Li-Shiuan Peh, Samadi, K.
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Architectural-level modeling
Chips
Clocks
Design engineering
design space exploration
Design. Technologies. Operation analysis. Testing
Electronics
Estimation
Exact sciences and technology
Fabrics
Integrated circuit modeling
Integrated circuits
Interconnection
Logic gates
Mathematical model
network-on-chip (NoC)
Networks
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Simulation
Switches
Transistors
Very large scale integration
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Beschreibung
Zusammenfassung:As industry moves towards multicore chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power has become crucially important. In this work, we present ORION 2.0, an enhanced NoC power and area simulator, which offers significant accuracy improvement relative to its predecessor, ORION 1.0.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2010.2091686