A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery

A digital clock and data recovery circuit (CDR) employs hybrid analog/digital phase detection to achieve linear loop dynamics and to eliminate the nonlinearity and quantization error of a bang-bang phase detector. The proposed architecture achieves constant jitter transfer bandwidth independent of input data jitter and reduces the sensitivity to digitally-controlled oscillator's frequency quantization error and consecutive identical digits. The hybrid phase detection scheme also helps decouple jitter generation from jitter transfer characteristics of the CDR. The proto-type digital CDR fabricated in 0.13 μm CMOS technology achieves error-free operation (BER