Stochastic Networked Computation
In this paper, the stochastic networked computation (SNC) paradigm for designing robust and energy-efficient systems-on-a-chip in nanoscale process technologies, where robust computation is treated as a statistical estimation problem is presented. The benefits of SNC are demonstrated by employing it...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2010-10, Vol.18 (10), p.1421-1432 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Varatkar, Girish Vishnu Narayanan, Sriram Shanbhag, Naresh R Jones, Douglas L |
| description | In this paper, the stochastic networked computation (SNC) paradigm for designing robust and energy-efficient systems-on-a-chip in nanoscale process technologies, where robust computation is treated as a statistical estimation problem is presented. The benefits of SNC are demonstrated by employing it to design an energy-efficient and robust pseudonoise-code acquisition system for the wireless CDMA2000 standard (http://www.3gpp2.org). Simulations in IBM's 130-nm CMOS process show that the SNC-based architecture enhances the average probability of detection (P Det ) in the presence of process variations by two to three orders of magnitude, reduces power by 31%-39%, and reduces the variation in P Det by one to two orders of magnitude at a typical false-alarm rate of 5% over a conventional architecture. SNC performance in the presence of voltage overscaling and across technology nodes (90, 65, 45, and 32 nm) is also studied. |
| doi_str_mv | 10.1109/TVLSI.2009.2024673 |
| format | Article |
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The benefits of SNC are demonstrated by employing it to design an energy-efficient and robust pseudonoise-code acquisition system for the wireless CDMA2000 standard (http://www.3gpp2.org). Simulations in IBM's 130-nm CMOS process show that the SNC-based architecture enhances the average probability of detection (P Det ) in the presence of process variations by two to three orders of magnitude, reduces power by 31%-39%, and reduces the variation in P Det by one to two orders of magnitude at a typical false-alarm rate of 5% over a conventional architecture. SNC performance in the presence of voltage overscaling and across technology nodes (90, 65, 45, and 32 nm) is also studied.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2009.2024673</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Architecture ; CMOS ; CMOS process ; CMOS technology ; Code division multiple access (CDMA) ; Computation ; Computational modeling ; Computer architecture ; Computer networks ; Design. Technologies. Operation analysis. Testing ; Electronics ; Energy efficiency ; Exact sciences and technology ; Integrated circuits ; low power ; Nanocomposites ; Nanomaterials ; nanoscale ; Nanostructure ; Probability ; process variations ; reliability ; robust ; Robustness ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; soft errors ; stochastic ; Stochastic processes ; Stochastic systems ; Stochasticity ; Very large scale integration ; Voltage</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2010-10, Vol.18 (10), p.1421-1432</ispartof><rights>2015 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Oct 2010</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c357t-f8a70899b5f09da26e363d625b8251afc9bd163ab31750c711ab92e19d07df7e3</citedby><cites>FETCH-LOGICAL-c357t-f8a70899b5f09da26e363d625b8251afc9bd163ab31750c711ab92e19d07df7e3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5280185$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,793,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5280185$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=23270490$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Varatkar, Girish Vishnu</creatorcontrib><creatorcontrib>Narayanan, Sriram</creatorcontrib><creatorcontrib>Shanbhag, Naresh R</creatorcontrib><creatorcontrib>Jones, Douglas L</creatorcontrib><title>Stochastic Networked Computation</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>In this paper, the stochastic networked computation (SNC) paradigm for designing robust and energy-efficient systems-on-a-chip in nanoscale process technologies, where robust computation is treated as a statistical estimation problem is presented. The benefits of SNC are demonstrated by employing it to design an energy-efficient and robust pseudonoise-code acquisition system for the wireless CDMA2000 standard (http://www.3gpp2.org). Simulations in IBM's 130-nm CMOS process show that the SNC-based architecture enhances the average probability of detection (P Det ) in the presence of process variations by two to three orders of magnitude, reduces power by 31%-39%, and reduces the variation in P Det by one to two orders of magnitude at a typical false-alarm rate of 5% over a conventional architecture. SNC performance in the presence of voltage overscaling and across technology nodes (90, 65, 45, and 32 nm) is also studied.</description><subject>Applied sciences</subject><subject>Architecture</subject><subject>CMOS</subject><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Code division multiple access (CDMA)</subject><subject>Computation</subject><subject>Computational modeling</subject><subject>Computer architecture</subject><subject>Computer networks</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Energy efficiency</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>low power</subject><subject>Nanocomposites</subject><subject>Nanomaterials</subject><subject>nanoscale</subject><subject>Nanostructure</subject><subject>Probability</subject><subject>process variations</subject><subject>reliability</subject><subject>robust</subject><subject>Robustness</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>soft errors</subject><subject>stochastic</subject><subject>Stochastic processes</subject><subject>Stochastic systems</subject><subject>Stochasticity</subject><subject>Very large scale integration</subject><subject>Voltage</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2010</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkEtLAzEQgIMoWKt_QC8FEU9bJ8nmdZTio1D00Oo1ZLNZ3Lrd1GQX8d-b2qUH5zAzMN8Mw4fQJYYpxqDuVu-L5XxKAFRKJOeCHqERZkxkKsVx6oHTTBIMp-gsxjUAznMFIzRZdt5-mNjVdvLium8fPl05mfnNtu9MV_v2HJ1UponuYqhj9Pb4sJo9Z4vXp_nsfpFZykSXVdIIkEoVrAJVGsId5bTkhBWSMGwqq4oSc2oKigUDKzA2hSIOqxJEWQlHx-h2f3cb_FfvYqc3dbSuaUzrfB-1ZIwrCixP5PU_cu370KbnNAaiJJcYaKLInrLBxxhcpbeh3pjwkyC9c6b_nOmdMz04S0s3w2kTrWmqYFpbx8MmoURA0pa4qz1XO-cOY0YkYMnoL9OBcv8</recordid><startdate>20101001</startdate><enddate>20101001</enddate><creator>Varatkar, Girish Vishnu</creator><creator>Narayanan, Sriram</creator><creator>Shanbhag, Naresh R</creator><creator>Jones, Douglas L</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Solid state devices</topic><topic>soft errors</topic><topic>stochastic</topic><topic>Stochastic processes</topic><topic>Stochastic systems</topic><topic>Stochasticity</topic><topic>Very large scale integration</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Varatkar, Girish Vishnu</creatorcontrib><creatorcontrib>Narayanan, Sriram</creatorcontrib><creatorcontrib>Shanbhag, Naresh R</creatorcontrib><creatorcontrib>Jones, Douglas L</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Varatkar, Girish Vishnu</au><au>Narayanan, Sriram</au><au>Shanbhag, Naresh R</au><au>Jones, Douglas L</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Stochastic Networked Computation</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2010-10-01</date><risdate>2010</risdate><volume>18</volume><issue>10</issue><spage>1421</spage><epage>1432</epage><pages>1421-1432</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>In this paper, the stochastic networked computation (SNC) paradigm for designing robust and energy-efficient systems-on-a-chip in nanoscale process technologies, where robust computation is treated as a statistical estimation problem is presented. The benefits of SNC are demonstrated by employing it to design an energy-efficient and robust pseudonoise-code acquisition system for the wireless CDMA2000 standard (http://www.3gpp2.org). Simulations in IBM's 130-nm CMOS process show that the SNC-based architecture enhances the average probability of detection (P Det ) in the presence of process variations by two to three orders of magnitude, reduces power by 31%-39%, and reduces the variation in P Det by one to two orders of magnitude at a typical false-alarm rate of 5% over a conventional architecture. SNC performance in the presence of voltage overscaling and across technology nodes (90, 65, 45, and 32 nm) is also studied.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2009.2024673</doi><tpages>12</tpages></addata></record> |
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| subjects | Applied sciences Architecture CMOS CMOS process CMOS technology Code division multiple access (CDMA) Computation Computational modeling Computer architecture Computer networks Design. Technologies. Operation analysis. Testing Electronics Energy efficiency Exact sciences and technology Integrated circuits low power Nanocomposites Nanomaterials nanoscale Nanostructure Probability process variations reliability robust Robustness Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices soft errors stochastic Stochastic processes Stochastic systems Stochasticity Very large scale integration Voltage |
| title | Stochastic Networked Computation |
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