Dynamically trace scheduled VLIW architectures

Dynamically trace scheduled VLIW architectures

This paper presents a new architecture organisation, the dynamically !race scheduled VLIW (DTSVLIW), that can be used to implement machines that execute the code or current RISC or CISC instruction set architectures in a VLIW fashion, with backward code compatibility.

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Bibliographische Detailangaben
Hauptverfasser: de Souza, Alberto Ferreira, Rounce, Peter
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Applied sciences
Architecture
Computer science
control theory
systems
Computer systems
Computer systems and distributed systems. User interface
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Hardware
Integrated circuits
scheduling
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Software
Superscalar
trace cache
VLIW
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Beschreibung
Zusammenfassung:This paper presents a new architecture organisation, the dynamically !race scheduled VLIW (DTSVLIW), that can be used to implement machines that execute the code or current RISC or CISC instruction set architectures in a VLIW fashion, with backward code compatibility.
ISSN:0302-9743
1611-3349
DOI:10.1007/BFb0037255